1. Field of the Invention
The present invention relates to a bus interfacing circuit for a FIFO (first-in first-out) memory, and more particularly to a bus interfacing circuit for permitting a unilateral read/write FIFO memory to perform FIFO functions without a data bumping occurring when operated in bilateral data buses.
2. Description of the Conventional Art
FIG. 1 shows a conventional circuit for controlling a FIFO memory, consisting of a first and second ripple counter 1, 2 for respectively counting the numbers of bits belonging to a write signal and a read signal, a subtracter 3 for generating a difference between the counting values generating from the counters 1, 2, a decoder 4 for decoding an output signal of the subtracter 3 in accordance with the write signal and thereby generating a write enable signal and a read enable signal which are each of 16 bits, a comparator 5 for comparing the output signal of the subtracter 3 with a predetermined threshold level and thereby generating an empty signal or a full signal, a FIFO memory cell 6 for performing the FIFO function in response to the write and read enable signals generated from the decoder 4.
After initiating, an output value of 4 bits from the first ripple counter 1 is incremented in response to the rising of the write signal, simultaneously with an increment of an output value of 4 bits from the second ripple counter 2 in response to the read signal. Then, the subtracter 3 is activated to perform the subtracting function upon the counted signals so as to generate the difference between the counted write and read signals. The output signal of the subtracter 3 is compared with the threshold level in the comparator 5.
Up to this point, the comparator generates the empty signal until the voltage level of the output signal from the subtracter 3 becomes equal to the threshold level, all upon becoming equal to the threshold level the full signal is generated therefrom.
On the other hand, the output signal of the subtracter 3 is applied to the decoder 4 and synchronized with the write signal so that the write and read enable signals of 16 bits are generated therefrom to control the FIFO memory cell 6. At this point, since the FIFO memory cell 6 performs its access operation within a fixed address without moving the write and read points, it is possible to carry out the FIFO function by the corresponding write and read enable signals.
However, it may be anticipated that since the conventional circuit utilizes an architecture of the unilateral data bus, data bumping would occur in a dual data bus system. Furthermore, such a conventional circuit as shown in FIG. 1 must include means for controlling the external write and read signals so as to allow it to share a single memory unit.